x86 is a family of backward compatible instruction set architectures based on the Intel 8086 CPU and its Intel 8088 variant. The 8086 was introduced in 1978 as a fully 16-bit extension of Intel's 8-bit based 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to the Intel's 8086 processor ended in "86", including 80186, 80286, 80386 and 80486 processors.
Many additions and extensions have been added to the x86 instruction set over the years, almost consistently with full backward compatibility. The architecture has been implemented in processors from Intel, Cyrix, AMD, VIA and many other companies; there are also open implementations, such as the Zet SoC platform.
The term is not synonymous with IBM PC compatibility as this implies a multitude of other computer hardware; embedded systems as well as general-purpose computers used x86 chips before the PC-compatible market started, some of them before the IBM PC itself.
In the 1980s and early 1990s when the 8088 and 80286 were still in common use, the term x86 usually represented any 8086 compatible CPU. Today, however, x86 usually implies a binary compatibility also with the 32-bit instruction set of the 80386. This is due to the fact that this instruction set has become something of a lowest common denominator for many modern operating systems and probably also because the term became common after the introduction of the 80386 in 1985.
A few years after the introduction of the 8086 and 8088, Intel added some complexity to its naming scheme and terminology as the "iAPX" of the ambitious but ill-fated Intel iAPX 432 processor was tried on the more successful 8086 family of chips, applied as a kind of system-level prefix. An 8086 system, including coprocessors such as 8087 and/or 8089, as well as simpler Intel-specific system chips, was thereby described as an iAPX 86 system. There were also terms iRMX (for operating systems), iSBC (for single-board computers), and iSBX (for multimodule boards based on the 8086-architecture) – all together under the heading Microsystem 80. However, this naming scheme was quite temporary, lasting for a few years during the early 1980s.
Although the 8086 was primarily developed for embedded systems and small multi-user or single-user computers, largely as a response to the successful 8080-compatible Zilog Z80,the x86 line soon grew in features and processing power. Today, x86 is ubiquitous in both stationary and portable personal computers, and is also used in midrange computers, workstations, servers and most new supercomputer clusters of TOP500 list. A large amount of software, including operating systems (OSs) such as DOS, Windows, Linux, BSD, Solaris and Mac OS X, functions with x86-based hardware.
Modern x86 is relatively uncommon in embedded systems, however, and small low power applications (using tiny batteries) as well as low-cost microprocessor markets, such as home appliances and toys, lack any significant x86 presence. Simple 8-bit and 16-bit based architectures are common here, although the x86-compatible VIA C7, VIA Nano, AMD's Geode, Athlon Neo and Intel Atom are examples of 32- and 64-bit designs used in some relatively low power and low cost segments.
There have been several attempts, including by Intel itself, to end the market dominance of the "inelegant" x86 architecture designed directly from the first simple 8-bit microprocessors. Examples of this are the iAPX 432 (a project originally named the "Intel 8800"), the Intel 960, Intel 860 and the Intel/Hewlett-Packard Itanium architecture. However, the continuous refinement of x86 microarchitectures, circuitry and semiconductor manufacturing would make it hard to replace x86 in many segments. AMD's 64-bit extension of x86 (which Intel eventually responded to with a compatible design) and the scalability of x86 chips such as the eight-core Intel Xeon and 12-core AMD Opteron is underlining x86 as an example of how continuous refinement of established industry standards can resist the competition from completely new architectures.
The table below lists brands of common consumer targeted processors implementing the x86 instruction set, grouped by generations that emphasize important events of x86 history. Note: CPU generations are not strict - each generation is characterized by significantly improved or commercially successful processor microarchitecture designs.
|Generation||First introduced||Prominent consumer CPU brands||Linear/physical address space||Notable (new) features|
|1st||1978||Intel 8086, Intel 8088 and clones||16-bit / 20-bit||First x86 microprocessors|
|1982||Intel 80186, Intel 80188 and clones, NEC V20/V30||Hardware for fast address calculations, fast multiplication and division|
|2nd||Intel 80286 and clones||16-bit ((14+16)-bit segmented) / 24-bit||MMU, for protected mode and a larger address space|
|3rd (IA-32)||1985||Intel 80386 and clones, AMD Am386||32-bit ((14+32)-bit segmented) / 32-bit||32-bit instruction set, MMU with paging|
|3rd/4th||1992||Cyrix Cx486SLC, Cyrix Cx486DLC||L1 cache and pipelining introduced into the 386 platform|
|4th (FPU)||1989||Intel 80486 and clones, AMD Am486||RISC-like pipelining, integrated x87 FPU (80-bit), on-chip cache|
|4th/5th||1997||Am5x86, Cyrix 5x86, Pentium OverDrive||Partial Pentium's specification brought into the 486 platform|
|5th||1993||Pentium, Pentium MMX, Rise mP6||Superscalar 64-bit databus, faster FPU, MMX (2× 32-bit)|
|5th/6th||1996||AMD K5, Cyrix 6x86, Cyrix MII, Nx586 (1994), IDT/Centaur-C6, Cyrix III-Samuel, VIA C3-Samuel2 / VIA C3-Ezra (2001)||Discrete microarchitecture (?-op translation)|
|6th||1997||AMD K6/2/III||L3-cache support, 3DNow!|
|1995||Pentium Pro, Cyrix III-Joshua (2000)||As above / 36-bit physical (PAE)||?-op translation, conditional move instructions, Out-of-order register renaming, speculative execution, PAE (Pentium Pro), in-package L2 cache (Pentium Pro)|
|1997||Pentium II/III||SSE (2× 64-bit)|
|6th/7th||2003||Pentium M, VIA C7 (2005), Intel Core (2006)||Optimized for low thermal design power, four pumped FSB|
|7th||1999||Athlon, Athlon XP||Superscalar FPU, wide design (up to three x86 instr./clock)|
|2000||Pentium 4||Deeply pipelined, high frequency, SSE2, hyper-threading|
|7/8th||2004||Pentium 4 Prescott, Pentium D||64-bit / 40-bit physical||Very deeply pipelined, very high frequency, SSE3, 64-bit capability (integer CPU) in LGA 775 sockets, CMT|
|8th||2006||Intel Core 2||64-bit (integer CPU), low power, multi-core, lower clock frequency, SSE4 (Penryn), wide dynamic execution, ?-op fusion, macro-?-op fusion|
|2008||VIA Nano||Out-of-order, superscalar, 64-bit (integer CPU), hardware-based encryption; very low power; adaptive power management|
|2003||Athlon 64, Opteron||As above / 40-bit physical||x86-64 instruction set (CPU main integer core), on-die memory controller, HyperTransport|
|2007||AMD Phenom, AMD Phenom II (2008)||As above / 48-bit physical||Monolithic quad-core, SSE4a, HyperTransport 3|
|8th/9th||2008||Intel Core i3, Core i5 and Core i7||As above / 40-bit physical||QuickPath, native memory controller, on-die L3 cache, modular, GPGPU introduced onto CPU chip|
|Intel Atom||In-order but highly pipelined, very-low-power, some models with 32-bit (integer CPU), on-die GPU|
|2011||AMD Bobcat||Out-of-order, 64-bit (integer CPU), on-die GPU; low power (Bobcat)|
|AMD Llano||As above / 48-bit physical|
|9th (GPU)||2011||AMD Bulldozer and Trinity||SSE5/AVX (4× 64-bit), highly modular design, integrated on-die GPU|
|Intel Sandy Bridge and Ivy Bridge||As above / 40-bit physical|
|2013||Intel Haswell||As above / 44-bit physical||AVX2, FMA3, TSX, BMI1, and BMI2 instructions|
|Others||2012||Intel Xeon Phi (Larrabee)||(MIC pilot) Many Integrated Cores (62), In-order P54C with x86-64, very wide vector unit, LRBni instructions (8× 64-bit)|
|2000||Transmeta Crusoe, Transmeta Efficeon||32-bit ((14+32)-bit segmented) / 32-bit||VLIW design with x86 emulator, on-die memory controller|
|2001||Intel Itanium IA-32 compatibility mode||32-bit ((14+32)-bit segmented) / N/A||EPIC architecture with an on-package engine (pre-2006 chips, later using IA-32 Execution Layer) that provides backward support for most IA-32 applications|